1. Field of the Invention
The invention relates to the field of electrically programmable read-only memories, particularly those employing floating gate memory devices.
2. Prior Art
Metal-oxide-semiconductor (MOS) electrically programmable read-only memories (EPROMs) frequently use memory cells that have electrically isolated gates (floating gates). These floating gates are typically completely surrounded by insulation and formed from a polycrystalline silicon (polysilicon) layer. Information is stored in the memory cells or devices in the form of charge on the floating gates. Charge is transported to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc., depending on the construction of the cells. The cells are erased generally by exposing the array to ultraviolet radiation. An example of these cells can be found in U.S. Pat. Nos. 3,500,142; 3,660,819; 3,755,721; and 4,099,196. In some cases these cells are electrically erasable (EEPROM cell). An example of such a cell is shown in U.S. Pat. No. 4,203,158.
The invention of the present application is used with an EPROM cell particularly one which is electrically erasable, referred to as a "flash" EPROM cell. The cell used with the present invention is described in copending application, Ser. No. 253,775, entitled Low Voltage EEPROM Cell, filed Oct. 5, 1988, and assigned to the assignee of the present invention.
It has been known for many years that when EPROM cells are used in a memory array, circuitry is sometimes required to electrically isolate the devices, one from the other. This may be needed, for example, to permit the reading of one cell without interference from adjacent cells, or for instance, to permit the programming of a cell without disturbing the programming of another cell. For examples of this, see U.S. Pat. Nos. 3,728,695 and 4,698,787.
The closest prior art known to Applicant is U.S. Pat. No. 4,698,787. This patent discloses the use of a cell having asymmetric source and drain regions in a memory array. Methods for providing selective erasing are described. (See column 11, beginning line 54 through column 12, through line 23.) This patent teaches the use of select transistors associated with the word lines for isolating, for example, bytes (see transistor 129 of FIG. 5d). As will be seen, the present invention provides block erasing in an array without use of isolation or other transistors activated by the word line of the array.